On a VLSI integrated circuit, such as a microprocessor, some signal lines may be routed adjacent to each other over relatively large distances (e.g., over several hundred microns). This may be necessary because the signals have a common source and destination; are part of a large multi-bit bus, or were coincidentally routed adjacent to each other by an automated router. Unfortunately, this arrangement causes problems that may lead to unreliable, or incorrect, functioning of the integrated circuit.
When at least one of the signal lines switches (the culprit) while at least one of the other signals is attempting to remain at its previous value (the victim), the capacitance between the signal lines will cause the victim line to “glitch” as charge is capacitively transferred between the culprit line(s) and the victim line. This “glitch” can cause failures when, for example, it causes the victim line to rise above a gate threshold voltage from ground, turning on an n-channel FET (field effect transistor) whose gate is connected to the victim line.
For dynamic receiver circuits, in certain circumstances, the culprit and victim lines are pre-charged to a supply voltage. As the culprit line transitions to ground from the supply voltage, a voltage drop in the victim line can occur due to the coupling capacitance between the culprit line and the victim line. This can cause a change in logic of the dynamic receiver circuit associated with the victim line. As a result, the dynamic receiver circuit associated with the victim line erroneously discharges.